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Preliminary Data Sheet
MAXIMUM ELECTRICAL DC CHARACTERISTICS
Rev.0.9
20.09.2011
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
V DDL Supply Voltage
Voltage on any pin relative to V SS
SYMBOL
V DD
V DDQ
V DDL
V IN , V OUT
MIN
-0.4
-0.4
-0.4
-0.4
MAX
1.975
1.975
1.975
1.975
UNITS
V
V
V
V
INPUT LEAKAGE CURRENT
Any input 0V ≤ V IN ≤ V DD, V REF pin 0V ≤ V IN ≤ 0.95V
(All other pins not under test = 0V)
Command/Address
RAS#, CAS#, WE#, S#, CKE
CK, CK#
DM
I I
-16
-16
-2
16
16
2
μA
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ V OUT ≤ V DDQ )
I OZ
-5
5
μA
DQ, DQS, DQS#
V REF LEAKAGE CURRENT ; V REF is on a valid level
I VREF
-8
8
μA
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
V DDL Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
V DD
V DDQ
V DDL
V REF
V TT
V IH (DC)
V IL (DC)
MIN
1.425
1.425
1.425
0.49 x V DDQ
0.49 x V DDQ -20mV
V REF + 0.1
-0.3
NOM
1.5
1.5
1.5
0.50 x V DDQ
0.50 x V DDQ
MAX
1.575
1.575
1.575
0.51x V DDQ
0.51x V DDQ +20mV
V DDQ + 0.3
V REF – 0.1
UNITS
V
V
V
V
V
V
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
V IH (AC)
V IL (AC)
MIN
V REF + 0.175
-
MAX
-
V REF - 0.175
UNITS
V
V
CAPACITANCE
At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 6
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